The layers in a layout represent the physical characteristics of the devices and have more details than schematics.
So, in the design flow of your circuit, verification with layout is critical.
We will use pcell developed NCSU to layout a simple inverter based on AMI 0.5µm technology.
1. To create layout view of our inverter, go to Library Manager and create a new cell view as Figure 22.
Figure 22. Creating layout view of inverter
2. With click OK, you will see two windows appear, one is LSW( Layer Selection Window) and the other is Virtuoso Layout Editing window, shown Figure 23.
Figure 23. LSW and Layout Editing window
3. To set the display so that all layers wiil appear, in Layout Editing window, select Options --> Display.
Set the options as Figure 24 and click OK.
Figure 24. Setting display options
Now, we will get nmos, ntap, pmos, ptap pcell.
4. In Layout Editing window, select Create --> Instance...
Click Browse in Create Instance window and select nmos in layout_macors according to Figure 25.
Figure 25. NMOS pcell
5. Put nmos pcell down in Layout Editing window like in Figure 26.
Figure 26. Placing the nmos pcell
6. Repeating the steps for ntap, pmos, ptap and m1_poly. And move the pcells around until looks like Figure 27.
Figure 27. Final placement of pcells
7. To draw power rails, click on metal 1(dg) in the LSW and go to Create --> Rectangle in the Layout Editing window.
And draw the power rails as in Figure 28.
Figure 28. Adding power rails
8. Add metal 1(dg) to ntap and source of the pmos for vdd! as ahown Figure 29.
Figure 29. Power connection to ntap and source of pmos
9. Add metal 1(dg) to ptap and source of the nmos for gnd! as in Figure 30.
Figure 30. Ground connection to ptap and source of nmos
10. Connect the drains of nmos and pmos with metal 1(dg) for output.
Figure 31. Connection the drains for output
11. To connect gate of devices, change to the poly layer in LSW and add a connection to gate of two transistors like in Figure 32.
Figure 32. Connecting gate of transistors
12. Now, add a ploy connection to the m1_poly via as Figure 33 This is your completed layout without pins.
Figure 33. Completed layout of inverter without pins
In order to simulate your extracted view of laid out inverter, you need to add four pins, vdd!, gnd!, A and Y.
The symbol "!" means that the variable name is global.
13. Go to Create --> Pin... in the Layout Editing window and fill out like in Figure 34.
Figure 34. Pin creation
14. Place vdd! pin in the metal power bar on the pmos and gnd! pin in the metal power bar on the nmos.
And, change I/O type in Create Symbolic Pin window to input for A and output for Y.
Then, place A in the metal region connecting drain of devices and Y in the m1_poly via.
The completed layout of inverter should look like Figure 35.
Figure 35. Completed inverter layout
Now, you are ready for DRC (Design Rule Checking).
