String passing example

1) For illustration strings are used;
But strings can’t be used in module ports;
2) Use SystemVerilog “program” instead of “module” for testbenches.
See this: SystemVerilog program example

//  dpi_top.v

module top ();

import "DPI-C" context v2c_c=

task v2c_sv(input string a);

import "DPI-C" context c2v_c=

function string c2v_sv();

export "DPI-C" print_string_c =

function print_string_sv;

string v2c_string,c2v_string;

function void

print_string_sv(input string aaa);

$display("Exporting VerilogFunction:%s", aaa);

endfunction

initial

begin

v2c_string = "A v2c_string";

v2c_sv(v2c_string);

c2v_string = c2v_sv();

$display("c2v_string: %s n",

c2v_string);

$finish;

end

endmodule

//  dpi_main.c

#include <stdio.h>

#include "svdpi.h"

#include "dpi.h"

#include "veriuser.h"

void v2c_c(char* v2c_string)

{

io_printf("v2c_string: %sn",v2c_string);

print_string_c("string passed from C");

}

char* c2v_c(void)

{

char* c2v_string;

c2v_string="This is c2v_string";

//io_printf("c2v_string: %sn",

//c2v_string);

return c2v_string;

}

#####   shell script to run simulation

 ncverilog +sv dpi_top.v +elaborate +ncelabargs+-messages

 gcc -fPIC -shared -o dpi_main.so  dpi_main.c  -I/$CDS_INST_DIR/tools.lnx86/inca/include

 ncverilog +sv dpi_top.v +sv_lib=dpi_main.so +access+r +ncsimargs+"-sv_root ./"