动态仿真仅仅适用于在RTL level验证design的功能，不适合验证gate level netlist，因为testbench不能覆盖所有的data path。但是这种方法依然得到广泛的应用。

The SDF file contains timing information of each cell in the design. The basic timing data comprises of the following'

• IOPATH delay
• INTERCONNECT delay
• SETUP timing check
• HOLD timing check

IOPATH delay specifies the cell delay.Its computation is based upon the output wire loading and the transition time of the input signal.

INTERCONNECT delay is a path based, point to point delay, which accounts for the RC delay between the driving gate and the driven agate. This wire delay is specified from the output pin of the driving cell to the input pin of the driven cell.

The SETUP and HOLD timing checks contain values that determine the reuqired setup and hold time of each sequential cell. These numbers are based upon the characterized values in the technology library.

SDF File Generation

The SDF file may be generated for pre-layout or post-layout simulations. The post SDF file is generated from DC or PT, after back annotating the extracted RC delay values and parasitic capacitances, to DC or PT. The post-layout values thus represent the actual delays associated with the design.

• DC command: write_timing -format sdf -v2.1 -output <filename>
• PT command: writesdf -version [1.0 or 2.1] <filename>

the pre-layout netlist does not contain the clock tree. In order to generate the pre-layout SDF, the following commands approximate the post-route clock tree values by defining the clock delay,skew and the transition time.

DC & PT commands

• create_clock -period 30 -waveform [list 0 15][list CLK]
• set_clock_latency 2.0 [get_clocks CLK]
• set_clock_transition 0.2 [get_clocks CLK]

DC only uses the above commands to perform STA, and does not output this information to the SDF file.

before layout, there are not clock tree buffers. there usually is a buffer/cell at the clock source. this cell may be a big driver or an input pad. At the pre-layout level, the output pin Z connects directly to all the endpoints.

The easy way to fix the SDF(to reflect the 2.0 ns clock delay from source CLK to all the endpoints) is to replace the delay value of the shaded cell(A->Z) calculated by DC with 2.0ns by

DC command 

• dc_shell -t> set_annotated_delay 2.0 -cell \
•                    -from CLKPAD/A -to CLKPAD/Z

This delay is reflected in the SDF file in the form of IOPATH delay(cell delay), for the cell CLKPAD, from pin A to pin Z.

DC uses the fixed transition value of the clock to calculate delays of driven gates.

Generating Post-Layout SDF File

The post-layout design contains the clock tree information. Only the extracted parasitic capacitances and RC delays should be back annotated to DC or PT, for final SDF generation. The following commands may be used to back annotated the extracted data to the design and specify the clock information while generating the post-layout SDF file for simulation:

DC & PT command

• read_sdf <interconnect RC`s in SDF format>
• source <parasitic capacitances in set_load format>
• read_parasitics <DSPF,RSPF ot SPEF file for clocks + other critical nets>
• create_cllock -period 30 -waveform [list 0 15][list CLK]
• set_propagated_clock [get_clocks CLK]

Issues Related to Timing Checks

To prevent these problems, one may need to falsify selectively, the value of the setup and hold-time constructs in the SDF file, for simulation to succeed.

DC & PT command

• dc_shell -t > set_annotated_check 0 -setup -hold   \
•                                                    -from REG1/CLK  \
•                                                    -to REG1/D    \

 The delay calculation of a cell is based on the input transition time and the outut load capacitance of a cell. The input transition time of a cell  is evaluated based on the transition delay of the driving cell (previous cell). Suppose that the signal reset is not critical and signal_a is critical. DC uses the worst (maximum) transition value of the preceding gate (U1) as the input transition time for the driven gate (U2).

So the 2ns will be used as input transition time for U2. This causes a large delay value to be computed for cell U2.

To avoid this problem, one needs to instruct DC not to perform the delay calculation for the timing arc from A to pin Z of U1.

DC command

• dc_shell -t> set_disable_timing U1 -from A -to Z